The present invention relates to processing of a semiconductor device, and more particularly, but not exclusively relates to a technique to provide metallization for interconnecting local connection regions along the substrate of a semiconductor device and simultaneously forming gate electrodes.
Most Integrated Circuits (ICs) require some type of metallic interconnection. For highly integrated semiconductors, these interconnections are often provided by depositing an Intermetal Oxide (IMO) layer over a semiconductor substrate bearing the various components to be interconnected, and then etching a via hole through the oxide layer to form a metallic contact with the contact region of each component. These metal contact vias are typically connected by metal lines formed on the top side of the IMO in accordance with a routing pattern. When extensive interconnections are required, connection routing on the top side of the IMO layer may become complex. Also, the smaller semiconductor component features become, the more difficult it is to properly align a large number of contact vias. This problem is particularly prominent in the development of ICs with high density Random Access Memory (RAM).
Thus, a need exists to reduce IC interconnection routing complexity and the number of interconnecting contact vias required. The present invention satisfies this need and provides other significant benefits and advantages.